Ph.D Dissertation Defense Presentation by, Muhammad Yanhaona

yanhaonamuhammadDate: Friday, December 2, 2016 at 10:00AM in Rice 242
Advisor: Andrew Grimshaw
Committee: Kevin Skadron (Committee Chair), Jack Davidson, Westley Weimer and Mircea Stan (Electrical and Computer Engineering).

PCubeS Type Architecture and IT Programming Language

ABSTRACT:

As the rate of improvement of uniprocessors slows, parallel programming has become an issue for more programmers now, not just for high performance scientific computing developers. Multicore processors and accelerators are now ubiquitous in both small and large scale computing devices. The potential for performance improvement through parallelism is significant in contemporary hardware.

Despite the heightened interest towards parallel computing in recent years; writing efficient, portable parallel applications remains a challenge, in particular, in the presence of increasingly heterogeneous architectures. The predominant way of parallel computing is to extend a sequential language with low level parallelization primitives. These primitives are platform specific, difficult to combine, and often error-prone. Recent high level language based alternatives to these tools struggle to perform well and lack in portability also.

This research proposes an alternative parallel programming paradigm to strike a balance between existing platform specific and hardware agnostic approaches. The paradigm lets a program’s logic to be expressed over a generic machine abstraction, called PCubeS, to enable portability. The language counterpart, called IT, enables reasoning about hardware features in all aspects of programming but emphasizes on separation of concerns and uses a declarative syntax so that program efficiency can be achieved productively.

Three IT compilers have been developed for three architecture types (multicore CPUs, distributed memory machines, and hybrid supercomputers having both CPUs and NVIDIA GPUs as nodes) as part of this research. Early performance experiment results on representative hardware platforms for five well-known applications indicate that the proposed paradigm is a viable future option for portable and efficient parallel computing.

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